A Peripheral Component Interconnect Express (PCIe) bus is a third-generation input/output (I/O) local bus standard developed on a basis of a Peripheral Component Interconnect (PCI) bus and a PCI-X bus. A standard PCI Express system is a tree topology structure, and its major components include a root node (root complex, or RC), several switches (SW), and several terminal devices (referred to as endpoints, or EPs).
In a current phase, to break through a limitation that only a single RC can exist in a PCIe system and to implement sharing of a PCIe switching network by multiple hosts, a virtual switch mode (Virtual Switch Mode) technology is applied. That is, multiple SWs are virtualized in a PCIe SW, and each virtual switch (Virtual Switch) has an upstream port (upstream port) that connects to a host (Host) and has multiple downstream ports (downstream port) that connect to EP devices. Each Virtual Switch is completely independent of and isolated from each other. In a PCIe chip, it can be implemented that multiple upstream ports support multiple Hosts, port migration, and failover (Failover).
In a process of implementing embodiments of the present invention, the inventor finds that in the prior art, PCIe supports only a maximum of eight Hosts because a chip supports only a maximum of eight upstream ports. Therefore, due to the port limitation, sharing a PCIe switching network by more hosts still cannot be implemented.